1. Field of Invention
This invention relates to architecture of integrate circuits and operation thereof, and more particularly relates to a memory array structure that is suitably applied to a virtual-ground memory array, and to a method of operating a memory.
2. Description of Related Art
For non-volatile memory (NVM), a virtual ground array structure can be adopted to save the array area due to removal of device isolation. However, there are some drawbacks for the virtual-ground array if source side sensing is adopted in the reading.
FIG. 1 depicts a virtual-ground NVM array in the prior art. For, example, when the left side of the cell X1 is selected to read, the word line WLn is biased between the threshold voltages of two storage states, the select line SEL2 set high to pass the drain voltage Vd from the global bit line GBL0, and SEL1 set high to pass the source-side charging voltage which is used to judge the cell current 110. The global bit line GBL1 is charged from ground to a certain voltage (Vs) according to the magnitude of the cell current, and the sensing is done as GBL1 is at about 50-200 mV.
However, when the cells X2-X5 are all at the lower-Vt state, their channels are all turned on by the voltage on WLn so that a current path 120 is formed, through the select transistor coupled to SEL2 and the global bit line GBL2, to charge GBL2, and another current path 130 is also formed. The charging-induced voltage on GBL2 couples to the neighboring GBL1, so that the loading capacitance of GBL 1 is changed. As a result, wrong read behavior is easily caused, especially when the sensing window is narrower in a multi-level cell (MLC) application.
The variation of the loading capacitance can be reduced by setting more select lines and increasing the distance between the possibly charged global bit lines and the two global bit lines for reading. FIG. 2 depicts such a virtual-ground NVM array in the prior art. For example, when the left side of the cell X1 is to be read with the global bit lines GBL1 and GBL2 biased, a cell current 210 is formed, and two charging currents 220 and 230 may be formed. The nearest possibly charged global bit line is GBL5, which is quite distant from GBL2 and does not affect the latter if charged.
However, there is still considerable variation in GBL loading capacitance for the above memory array structure. For example, as shown in Table 1 below, when the left side of X1 is to be read, GBL1 is the source side, GBL2 is the drain side, and GBL0 neighboring to GBL1 is floated. When the left side of X3 is to be read, GBL3 is the source side, GBL0 is the drain side, GBL4 neighboring to GBL3 is floated, and GBL1 and GBL2 are floated. Accordingly, the source-side and drain-side GBL loading capacitances are changed when a different memory cell is to be read. Thus, wrong read behavior is still easily caused, especially when the sensing window is narrower in an MLC application.
TABLE 1GBL0GBL1GBL2GBL3GBL4GBL5GBL6GBL7Left side of X1aFVsVdFFFFFLeft side of X3VdFFVsFFFFa: F = Floated